diff -u gcc-5-5.3.1/debian/changelog gcc-5-5.3.1/debian/changelog --- gcc-5-5.3.1/debian/changelog +++ gcc-5-5.3.1/debian/changelog @@ -1,3 +1,22 @@ +gcc-5 (5.3.1-13ubuntu1) xenial; urgency=medium + + * Update the ibm branch to 20160324. + + -- Matthias Klose Thu, 24 Mar 2016 22:22:16 +0100 + +gcc-5 (5.3.1-13) unstable; urgency=medium + + * Update to SVN 20160323 (r234424, 5.3.1) from the gcc-5-branch. + - Fix PR target/70188 (parisc), PR ipa/70306, PR target/70325 (x86), + PR target/70327 (x86), PR ipa/70269, PR ipa/70161, PR target/70293 (x86), + PR c++/70209. + * Update the Linaro support to the 5-2016.03 snapshot. + - Fix PR target/70113 (AArch64), PR target/69894, PR target/69895, + PR target/62254, PR target/69610, PR target/69161, PR target/67896. + * Fix building from the ibm branch with glibc 2.23. + + -- Matthias Klose Thu, 24 Mar 2016 14:43:10 +0100 + gcc-5 (5.3.1-12ubuntu4) xenial; urgency=medium * Update to SVN 20160318 (r234355, 5.3.1) from the gcc-5-branch. diff -u gcc-5-5.3.1/debian/control gcc-5-5.3.1/debian/control --- gcc-5-5.3.1/debian/control +++ gcc-5-5.3.1/debian/control @@ -6,7 +6,7 @@ Uploaders: Matthias Klose Standards-Version: 3.9.7 Build-Depends: debhelper (>= 5.0.62), dpkg-dev (>= 1.17.11), - g++-multilib [amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32] , g++-4.9 [arm64] , + g++-multilib [amd64 armel armhf i386 kfreebsd-amd64 mips mips64 mips64el mipsel mipsn32 mipsn32el powerpc ppc64 s390 s390x sparc sparc64 x32] , g++-5 [arm64] , libc6.1-dev (>= 2.13-0ubuntu6) [alpha ia64] | libc0.3-dev (>= 2.13-0ubuntu6) [hurd-i386] | libc0.1-dev (>= 2.13-0ubuntu6) [kfreebsd-i386 kfreebsd-amd64] | libc6-dev (>= 2.13-0ubuntu6), libc6-dev (>= 2.13-31) [armel armhf], libc6-dev-amd64 [i386 x32], libc6-dev-sparc64 [sparc], libc6-dev-sparc [sparc64], libc6-dev-s390 [s390x], libc6-dev-s390x [s390], libc6-dev-i386 [amd64 x32], libc6-dev-powerpc [ppc64], libc6-dev-ppc64 [powerpc], libc0.1-dev-i386 [kfreebsd-amd64], lib32gcc1 [amd64 ppc64 kfreebsd-amd64 mipsn32 mipsn32el mips64 mips64el s390x sparc64 x32], libn32gcc1 [mips mipsel mips64 mips64el], lib64gcc1 [i386 mips mipsel mipsn32 mipsn32el powerpc sparc s390 x32], libc6-dev-mips64 [mips mipsel mipsn32 mipsn32el], libc6-dev-mipsn32 [mips mipsel mips64 mips64el], libc6-dev-mips32 [mipsn32 mipsn32el mips64 mips64el], libc6-dev-x32 [amd64 i386], libx32gcc1 [amd64 i386], libc6-dev-armhf [armel], libhfgcc1 [armel], libc6-dev-armel [armhf], libsfgcc1 [armhf], libc6.1-dbg [alpha ia64] | libc0.3-dbg [hurd-i386] | libc0.1-dbg [kfreebsd-i386 kfreebsd-amd64] | libc6-dbg, kfreebsd-kernel-headers (>= 0.84) [kfreebsd-any], linux-libc-dev [m68k], m4, libtool, autoconf2.64, diff -u gcc-5-5.3.1/debian/patches/ibm-branch.diff gcc-5-5.3.1/debian/patches/ibm-branch.diff --- gcc-5-5.3.1/debian/patches/ibm-branch.diff +++ gcc-5-5.3.1/debian/patches/ibm-branch.diff @@ -1,6 +1,6 @@ -# DP: updates from the ibm/5 branch upto 20160310 (r234119). +# DP: updates from the ibm/5 branch upto 20160324 (r234466). -svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@234111 svn://gcc.gnu.org/svn/gcc/branches/ibm/gcc-5-branch \ +svn diff svn://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@234461 svn://gcc.gnu.org/svn/gcc/branches/ibm/gcc-5-branch \ | sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \ | awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0' @@ -1730,7 +1730,7 @@ =================================================================== --- a/src/libgcc/config/rs6000/extendkftf2-sw.c (.../gcc-5-branch) +++ b/src/libgcc/config/rs6000/extendkftf2-sw.c (.../ibm/gcc-5-branch) -@@ -0,0 +1,49 @@ +@@ -0,0 +1,53 @@ +/* Software IEEE 128-bit floating-point emulation for PowerPC. + + Copyright (C) 2016 Free Software Foundation, Inc. @@ -1772,6 +1772,10 @@ +#include "soft-fp.h" +#include "quad-float128.h" + ++#ifndef FLOAT128_HW_INSNS ++#define __extendkftf2_sw __extendkftf2 ++#endif ++ +IBM128_TYPE +__extendkftf2_sw (__float128 value) +{ @@ -2078,9 +2082,30 @@ =================================================================== --- a/src/libgcc/ChangeLog.ibm (.../gcc-5-branch) +++ b/src/libgcc/ChangeLog.ibm (.../ibm/gcc-5-branch) -@@ -0,0 +1,90 @@ -+2016-02-26 Paul E. Murphy -+ Bill Schmidt +@@ -0,0 +1,114 @@ ++2016-03-24 Michael Meissner ++ ++ Merge up to 234461. ++ ++2016-03-22 Michael Meissner ++ ++ Backport from mainline ++ 2016-03-22 Michael Meissner ++ ++ PR libgcc/70363 ++ * config/rs6000/extendkftf2-sw.c (__extendkftf2_sw): If libgcc was ++ built with an assembler that does not support ISA 3.0 ++ instructions, rename __extendkftf2_sw to __extendkftf2. ++ ++2016-03-14 Michael Meissner ++ ++ Merge up to 234186. ++ ++2016-02-29 Bill Schmidt ++ ++ Backport from mainline ++ 2016-02-26 Paul E. Murphy ++ Bill Schmidt + + * config/rs6000/sfp-machine.h (_FP_DECL_EX): Declare _fpsr as a + union of u64 and double. @@ -2090,8 +2115,11 @@ + (FP_ROUNDMODE): Update the usage of _fpscr. + +2016-01-21 Michael Meissner -+ Steven Munroe -+ Tulio Magno Quites Machado Filho ++ ++ Backport from mainline ++ 2016-01-21 Michael Meissner ++ Steven Munroe ++ Tulio Magno Quites Machado Filho + + * config/rs6000/float128-sed: New files to convert TF names to KF + names for PowerPC IEEE 128-bit floating point support. @@ -3633,6 +3661,98 @@ +/* { dg-final { scan-assembler "load fusion, type DF" } } */ +/* { dg-final { scan-assembler "store fusion, type SF" } } */ +/* { dg-final { scan-assembler "store fusion, type DF" } } */ +Index: gcc/testsuite/gcc.target/powerpc/pr67071-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pr67071-1.c (.../gcc-5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr67071-1.c (.../ibm/gcc-5-branch) +@@ -0,0 +1,34 @@ ++/* { dg-do compile { target powerpc*-*-* } } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ ++/* { dg-options "-mcpu=power6 -maltivec" } */ ++ ++vector unsigned char ++foo_char (void) ++{ ++ return (vector unsigned char) { ++ 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, ++ 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 ++ }; ++} ++ ++vector unsigned short ++foo_short (void) ++{ ++ return (vector unsigned short) { ++ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000 ++ }; ++} ++ ++vector unsigned int ++foo_int (void) ++{ ++ return (vector unsigned int) { ++ 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, ++ }; ++} ++ ++/* { dg-final { scan-assembler-times "vspltisw" 3 } } */ ++/* { dg-final { scan-assembler-times "vslb" 1 } } */ ++/* { dg-final { scan-assembler-times "vslh" 1 } } */ ++/* { dg-final { scan-assembler-times "vslw" 1 } } */ +Index: gcc/testsuite/gcc.target/powerpc/pr67071-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pr67071-2.c (.../gcc-5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr67071-2.c (.../ibm/gcc-5-branch) +@@ -0,0 +1,48 @@ ++/* { dg-do compile { target powerpc*-*-* } } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ ++/* { dg-options "-mcpu=power6 -maltivec" } */ ++ ++vector unsigned char ++foo_char (void) ++{ ++ return (vector unsigned char) { ++#if __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__ ++ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++#else ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80 ++#endif ++ }; ++} ++ ++vector unsigned short ++foo_short (void) ++{ ++ return (vector unsigned short) { ++#if __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__ ++ 0x8000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 ++#else ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x8000 ++#endif ++ }; ++} ++ ++vector unsigned int ++foo_int (void) ++{ ++ return (vector unsigned int) { ++#if __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__ ++ 0x80000000u, 0x00000000u, 0x00000000u, 0x00000000u, ++#else ++ 0x00000000u, 0x00000000u, 0x00000000u, 0x80000000u, ++#endif ++ }; ++} ++ ++/* { dg-final { scan-assembler-times "vspltisw" 3 } } */ ++/* { dg-final { scan-assembler-times "vsldoi" 3 } } */ ++/* { dg-final { scan-assembler-times "vslb" 1 } } */ ++/* { dg-final { scan-assembler-times "vslh" 1 } } */ ++/* { dg-final { scan-assembler-times "vslw" 1 } } */ Index: gcc/testsuite/gcc.target/powerpc/p9-permute.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/p9-permute.c (.../gcc-5-branch) @@ -3712,11 +3832,83 @@ + +/* { dg-final { scan-assembler "lxvd2x 34" } } */ +/* { dg-final { scan-assembler "stxvd2x 34" } } */ +Index: gcc/testsuite/gcc.target/powerpc/pr67071-3.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pr67071-3.c (.../gcc-5-branch) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pr67071-3.c (.../ibm/gcc-5-branch) +@@ -0,0 +1,48 @@ ++/* { dg-do compile { target powerpc*-*-* } } */ ++/* { dg-require-effective-target powerpc_altivec_ok } */ ++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ ++/* { dg-options "-mcpu=power6 -maltivec" } */ ++ ++ ++vector unsigned char ++foo_char (void) ++{ ++ return (vector unsigned char) { ++#if __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__ ++ 0x80, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff ++#else ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x80 ++#endif ++ }; ++} ++ ++vector unsigned short ++foo_short (void) ++{ ++ return (vector unsigned short) { ++#if __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__ ++ 0x8000, 0x8000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff ++#else ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x8000, 0x8000 ++#endif ++ }; ++} ++ ++vector unsigned int ++foo_int (void) ++{ ++ return (vector unsigned int) { ++#if __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__ ++ 0x80000000u, 0x80000000u, 0xffffffffu, 0xffffffffu, ++#else ++ 0xffffffffu, 0xffffffffu, 0x80000000u, 0x80000000u, ++#endif ++ }; ++} ++ ++/* { dg-final { scan-assembler-times "vslb" 1 } } */ ++/* { dg-final { scan-assembler-times "vslh" 1 } } */ ++/* { dg-final { scan-assembler-times "vslw" 1 } } */ ++/* { dg-final { scan-assembler-times "vsldoi" 3 } } */ Index: gcc/testsuite/ChangeLog.ibm =================================================================== --- a/src/gcc/testsuite/ChangeLog.ibm (.../gcc-5-branch) +++ b/src/gcc/testsuite/ChangeLog.ibm (.../ibm/gcc-5-branch) -@@ -0,0 +1,126 @@ +@@ -0,0 +1,145 @@ ++2016-03-24 Michael Meissner ++ ++ Merge up to 234461. ++ ++2016-03-23 Michael Meissner ++ ++ Back port from mainline ++ 2015-08-12 Michael Meissner ++ ++ PR target/67071 ++ * gcc.target/powerpc/pr67071-1.c: New file to test PR 67071 new ++ vector constants. ++ * gcc.target/powerpc/pr67071-2.c: Likewise. ++ * gcc.target/powerpc/pr67071-3.c: Likewise. ++ ++2016-03-14 Michael Meissner ++ ++ Merge up to 234186. ++ +2016-02-04 Michael Meissner + + Backport from trunk @@ -4622,7 +4814,69 @@ =================================================================== --- a/src/gcc/ChangeLog.ibm (.../gcc-5-branch) +++ b/src/gcc/ChangeLog.ibm (.../ibm/gcc-5-branch) -@@ -0,0 +1,1073 @@ +@@ -0,0 +1,1135 @@ ++2016-03-24 Michael Meissner ++ ++ Merge up to 234461. ++ * REVISION: Update subversion id. ++ ++2016-03-23 Michael Meissner ++ ++ Back port from mainline ++ 2015-08-12 Michael Meissner ++ ++ PR target/67071 ++ * config/rs6000/predicates.md (easy_vector_constant_vsldoi): New ++ predicate to allow construction of vector constants using the ++ VSLDOI vector shift instruction. ++ ++ * config/rs6000/rs6000-protos.h (vspltis_shifted): Add ++ declaration. ++ ++ * config/rs6000/rs6000.c (vspltis_shifted): New function to return ++ the number of bytes to be shifted left and filled in with either ++ all zero or all one bits. ++ (gen_easy_altivec_constant): Call vsplitis_shifted if no other ++ methods exist. ++ (output_vec_const_move): On power8, generate XXLORC to generate ++ a vector constant with all 1's. Do a split if we need to use a ++ VSLDOI instruction. ++ ++ * config/rs6000/rs6000.h (EASY_VECTOR_MSB): Use mode mask to ++ properly test for the MSB. ++ ++ * config/rs6000/altivec.md (VSLDOI splitter): Add splitter for ++ vector constants that can be created with VSLDOI. ++ ++2016-03-23 Michael Meissner ++ ++ Back port from mainline ++ 2016-02-26 Jakub Jelinek ++ ++ PR target/69969 ++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't ++ complain about -mallow-movmisalign without -mvsx if ++ TARGET_ALLOW_MOVMISALIGN was not set explicitly. ++ ++2016-03-23 Michael Meissner ++ ++ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Move ++ setting wq/wp constraints to the same location as the trunk. ++ (rs6000_option_override_internal): Disable setting -mfloat128 ++ automatically if -mvsx. Add warnings from trunk for -mfloat128. ++ (rs6000_opt_masks): Add -mfloat128-hardware to be compatible with ++ trunk. ++ ++2016-03-18 Bill Schmidt ++ ++ * config/rs6000/rs6000.c (cpu_expand_builtin): Provide correct ++ number of arguments to gen_rtx_SET calls in code dependent on ++ glibc 2.23 or later. ++ ++2016-03-14 Michael Meissner ++ ++ Merge up to 234186. ++ +2016-03-10 Peter Bergner + + Merge up to 234111. @@ -6044,7 +6298,22 @@ if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) { if (zero_constant (op, mode)) -@@ -656,7 +764,7 @@ +@@ -561,6 +669,14 @@ + return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode)); + }) + ++;; Return true if this is an easy altivec constant that we form ++;; by using VSLDOI. ++(define_predicate "easy_vector_constant_vsldoi" ++ (and (match_code "const_vector") ++ (and (match_test "TARGET_ALTIVEC") ++ (and (match_test "easy_altivec_constant (op, mode)") ++ (match_test "vspltis_shifted (op) != 0"))))) ++ + ;; Return 1 if operand is constant zero (scalars and vectors). + (define_predicate "zero_constant" + (and (match_code "const_int,const_double,const_wide_int,const_vector") +@@ -656,7 +772,7 @@ ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct ;; moves are supported. (define_predicate "reg_or_indexed_operand" @@ -6053,7 +6322,7 @@ { if (MEM_P (op)) return indexed_or_indirect_operand (op, mode); -@@ -1739,6 +1847,35 @@ +@@ -1739,6 +1855,35 @@ return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; }) @@ -6089,7 +6358,7 @@ ;; Match the first insn (addis) in fusing the combination of addis and loads to ;; GPR registers on power8. (define_predicate "fusion_gpr_addis" -@@ -1761,8 +1898,6 @@ +@@ -1761,8 +1906,6 @@ else return 0; @@ -6098,7 +6367,7 @@ value = INTVAL (int_const); if ((value & (HOST_WIDE_INT)0xffff) != 0) return 0; -@@ -1770,6 +1905,12 @@ +@@ -1770,6 +1913,12 @@ if ((value & (HOST_WIDE_INT)0xffff0000) == 0) return 0; @@ -6111,7 +6380,7 @@ return (IN_RANGE (value >> 16, -32, 31)); }) -@@ -1835,13 +1976,14 @@ +@@ -1835,13 +1984,14 @@ ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the ;; memory field with both the addis and the memory offset. Sign extension ;; is not handled here, since lha and lwa are not fused. @@ -6130,7 +6399,7 @@ { op = XEXP (op, 0); mode = GET_MODE (op); -@@ -1862,6 +2004,12 @@ +@@ -1862,6 +2012,12 @@ return 0; break; @@ -6143,7 +6412,7 @@ default: return 0; } -@@ -1889,3 +2037,79 @@ +@@ -1889,3 +2045,79 @@ return 0; }) @@ -6305,7 +6574,15 @@ =================================================================== --- a/src/gcc/config/rs6000/rs6000-protos.h (.../gcc-5-branch) +++ b/src/gcc/config/rs6000/rs6000-protos.h (.../ibm/gcc-5-branch) -@@ -53,6 +53,9 @@ +@@ -31,6 +31,7 @@ + #endif /* TREE_CODE */ + + extern bool easy_altivec_constant (rtx, machine_mode); ++extern int vspltis_shifted (rtx); + extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); + extern bool macho_lo_sum_memory_operand (rtx, machine_mode); + extern int num_insns_constant (rtx, machine_mode); +@@ -53,6 +54,9 @@ extern const char *rs6000_output_move_128bit (rtx *); extern bool rs6000_move_128bit_ok_p (rtx []); extern bool rs6000_split_128bit_ok_p (rtx []); @@ -6315,7 +6592,7 @@ extern void rs6000_expand_vector_init (rtx, rtx); extern void paired_expand_vector_init (rtx, rtx); extern void rs6000_expand_vector_set (rtx, rtx, int); -@@ -82,7 +85,15 @@ +@@ -82,7 +86,15 @@ extern bool quad_load_store_p (rtx, rtx); extern bool fusion_gpr_load_p (rtx, rtx, rtx, rtx); extern void expand_fusion_gpr_load (rtx *); @@ -6331,7 +6608,7 @@ extern enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class); extern enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class, -@@ -133,8 +144,7 @@ +@@ -133,8 +145,7 @@ extern void rs6000_emit_le_vsx_move (rtx, rtx, machine_mode); extern void rs6000_emit_move (rtx, rtx, machine_mode); extern rtx rs6000_secondary_memory_needed_rtx (machine_mode); @@ -6341,7 +6618,7 @@ extern rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int, int, int *); extern bool rs6000_legitimate_offset_address_p (machine_mode, rtx, -@@ -191,6 +201,8 @@ +@@ -191,6 +202,8 @@ extern void rs6000_emit_load_toc_table (int); extern unsigned int rs6000_dbx_register_number (unsigned int, unsigned int); extern void rs6000_emit_epilogue (int); @@ -7126,14 +7403,16 @@ /* V2DF mode, VSX only. */ if (TARGET_VSX) { -@@ -2854,6 +3134,30 @@ +@@ -2854,6 +3134,25 @@ if (TARGET_LFIWZX) rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */ -+ /* Float128 support is not (yet) back ported to GCC 5.x, so the wp/wq -+ constraints are just ignored for now. */ -+ rs6000_constraints[RS6000_CONSTRAINT_wp] = NO_REGS; -+ rs6000_constraints[RS6000_CONSTRAINT_wq] = NO_REGS; ++ if (TARGET_FLOAT128) ++ { ++ rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */ ++ if (FLOAT128_IEEE_P (TFmode)) ++ rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */ ++ } + + /* Support for new D-form instructions. */ + if (TARGET_P9_DFORM) @@ -7147,17 +7426,10 @@ + if (TARGET_DIRECT_MOVE_128) + rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS; + -+ if (TARGET_FLOAT128) -+ { -+ rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */ -+ if (FLOAT128_IEEE_P (TFmode)) -+ rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */ -+ } -+ /* Set up the reload helper and direct move functions. */ if (TARGET_VSX || TARGET_ALTIVEC) { -@@ -2873,6 +3177,8 @@ +@@ -2873,6 +3172,8 @@ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load; reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store; reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load; @@ -7166,7 +7438,7 @@ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; -@@ -2880,6 +3186,12 @@ +@@ -2880,6 +3181,12 @@ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store; reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load; @@ -7179,7 +7451,7 @@ /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are available. */ if (TARGET_NO_SDMODE_STACK) -@@ -2894,7 +3206,7 @@ +@@ -2894,7 +3201,7 @@ reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load; } @@ -7188,7 +7460,7 @@ { reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti; reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti; -@@ -2933,6 +3245,8 @@ +@@ -2933,6 +3240,8 @@ reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load; reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store; reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load; @@ -7197,7 +7469,7 @@ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; -@@ -2940,6 +3254,12 @@ +@@ -2940,6 +3249,12 @@ reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store; reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load; @@ -7210,7 +7482,7 @@ /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are available. */ if (TARGET_NO_SDMODE_STACK) -@@ -2969,6 +3289,130 @@ +@@ -2969,6 +3284,130 @@ reg_addr[SFmode].scalar_in_vmx_p = true; } @@ -7341,7 +7613,7 @@ /* Precalculate HARD_REGNO_NREGS. */ for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r) for (m = 0; m < NUM_MACHINE_MODES; ++m) -@@ -3003,9 +3447,9 @@ +@@ -3003,9 +3442,9 @@ machine_mode m2 = (machine_mode)m; int reg_size2 = reg_size; @@ -7354,7 +7626,7 @@ reg_size2 = UNITS_PER_FP_WORD; rs6000_class_max_nregs[m][c] -@@ -3362,7 +3806,22 @@ +@@ -3362,7 +3801,22 @@ if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; else if (have_cpu) @@ -7378,30 +7650,7 @@ else { size_t i; -@@ -3532,12 +3991,32 @@ - | OPTION_MASK_DIRECT_MOVE) - & ~rs6000_isa_flags_explicit); - -+ /* At present, we only build the __float128 emulator on PowerPC Linux. -+ Enable default __float128 support for PowerPC Linux systems, but not for -+ others. */ -+#ifdef POWERPC_LINUX -+ if (TARGET_VSX && !TARGET_FLOAT128 -+ && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128) == 0) -+ rs6000_isa_flags |= OPTION_MASK_FLOAT128; -+#endif -+ -+ /* __float128 requires VSX support. */ -+ if (TARGET_FLOAT128 && !TARGET_VSX) -+ { -+ if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128) != 0) -+ error ("-mfloat128 requires VSX support"); -+ -+ rs6000_isa_flags &= ~OPTION_MASK_FLOAT128; -+ } -+ - if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) - rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags); +@@ -3537,7 +3991,9 @@ /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-